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fn8272 rev 1.00 page 1 of 24 september 23, 2013 fn8272 rev 1.00 september 23, 2013 isl8115 high voltage synchronous buck pwm controller with integrated ga te driver and current sharing capability datasheet the isl8115 is a synchronous buck pwm controller with current sharing capability. the cu rrent sharing function allows multiple modules to be connected in parallel to achieve higher output current and to reduce input and output ripple current, resulting in fewer components and reduced output dissipation. utilizing voltage-mode control with input voltage feed-forward compensation, the isl8115 mainta ins a constant loop gain for optimal transient response, especi ally for applications with a wide input voltage range. the isl8115 protects against overcurrent conditions by inhibiting the pwm operation while monitoring the current with dcr of the output inductor, or a precision resistor. it also has a pre-por overvoltage protection option, which provides some protection to the load if the upper mosfet(s) is shorted. the isl8115 features remote ground sensing, programmable input voltage uvlo, output under/overvoltage protection, power-good indication, and fault hand shake capability. applications ? power supply for datacom/telecom and pol ? wide input voltage range buck regulators ? high current density power supplies rf power amplifier bias compensation features ?wide v in range operation: 2.97v to 36v; up to 5.5v output and 30a load current per phase ? fast transient response - voltage-mode pwm leading-edge modulation with non-linear control -input voltage feed-forward ? integrated 5v high speed 4a mosfet gate drivers - internal bootstrap diode ? excellent output voltage regulation - 0.6v 1.0% internal reference (-40c ~ 125c) - 0.6v 0.7% internal reference (-40c ~ 105c) - differential voltage sensing ? excellent current balancing and overcurrent protection - peak and average overcurrent protection - output current monitor on the iset pin ? oscillator programmable from 150khz to 1.5mhz - frequency synchronization to external clock signal ? diode emulation mode for light load efficiency improvement ? power-good open drain output ? pre-bias start-up function ?output ovp, uvp; otp ? adjustable soft-start u1 isl8115frtz iset 19 ishare 20 rg nd 1 6 ram p 5 pll_comp 21 vin 7 conf 22 ss 24 clkout 23 f b 1 7 v cc 3 e n 2 i s e nb 1 4 v m o n 1 5 f s e t 1 p g o o d 4 v f f 6 ugate 9 phase 10 pvcc 11 lgate 12 i s e na 1 3 boot 8 co m p 1 8 gnd 25 cvin 2.2f rvin 2 ? rff_h 33.2k qh 3 1 2 4 5 ql 2*rjk0301 3 1 2 4 5 lout 320nh, 0.53m ? , pa1513-321 2 1 r f f _ l 4.12k cboot 0.22f rpcc 2.2 ? cpvcc 4.7f cvin1 4*10f vin rram p 140k cv cc 2.2f ren_u 68.1k ren_l 10k rfset 113k rss 18.2k rconf 11.8k 1.5v/30a 10v-15v cfb2 33nf rfb2 787 ros1 2k 390pf rpll 5.11k cpll 2.2nf ri s e t 10k ci s e t 1nf r 2.8k c 0.22f rfb1 3k ros 2k cfb3 8.2nf rfb3 49.9 ? rfb3 3k cfb1 2.2nf cout 2*6tpf330m9l; vout r i s e n 1.27k cp l l _ h 2*rjk0305 4*100f; 4*1 figure 1. typical application circuit, 10v-15v input, 1.5v/30a output
isl8115 fn8272 rev 1.00 page 2 of 24 september 23, 2013 table of contents application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 functional pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 enable and input voltage uvlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pre-bias startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 setting conf pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 setting ss pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 voltage feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 non linear control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 undervoltage and overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 por overvoltage protection (por-ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 over-temperature protection (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 inductor current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 peak current limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 average overcurrent protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 dem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 current sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 feedback compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 modulator break frequency equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 compensation break frequency equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 general powerpad design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
isl8115 fn8272 rev 1.00 page 3 of 24 september 23, 2013 application diagrams figure 2. typical application circuit, 24v-36v input, 5v/20a output 5v/20a 24v-36v rfset 113k cv c c 2.2f rfb1 14.7k ros1 2k lout 2.6 ? h, 1.58m ? , 7443556260 2 1 cpvc c 4.7f c 0.22f rfb3 133 ? cvin1 2*10f; 2*16sepc270mx r 7.15k cfb3 3.3nf cfb1 100pf rvin 2 ? 19 20 1 6 5 21 7 22 24 23 1 7 3 2 1 4 1 5 1 4 6 9 10 11 12 1 3 8 1 8 25 rfb3 14.7k rss 18.2k qh bsc 03906ns 3 1 2 4 5 ros 2k ri s e t 10.5k rff_h 33.2k cout 2*6tpf330m9l; cboot 0.22f ri s e n 3k rf f _ l 3k ren_u 174k ql bsc 03906ns 3 1 2 4 5 rconf 11.8k ci s e t 1nf cpll 2.2nf rfb2 13k cvin 2.2f ren_l 10k cp l l _ h 390pf rpll 5.11k rram p 140k rpcc 2.2 ? vin cfb2 4.7nf vout 4*100f; 4*1f u1 isl8115frtz iset ishare r g n d ram p pll_comp vin conf ss clkout f b v cc e n i s e n b v m o n f s e t p g o o d v f f ugate phase pvcc lgate i s e n a boot c o m p gnd
isl8115 fn8272 rev 1.00 page 4 of 24 september 23, 2013 figure 3. 2-phase, 10v-15v input, 1.5v/60a output application diagrams (continued) 1.5v/2*30a 10v-15v rfset 113k ros1 2k rfb1 3k cv cc 2.2f c 0.22f cpvcc 4.7f lout 320nh, 0.53m ? , pa1513-321 2 1 cvin1 4*10f rfb3 49.9 ? r 2.8k rvin 2 ? cfb1 2.2nf cfb3 8.2nf rss 18.2k rfb3 3k 19 20 1 6 5 21 7 22 24 23 1 7 3 2 1 4 1 5 1 4 6 9 10 11 12 1 3 8 1 8 25 rff_h 33.2k ri s e t 10k ros 2k qh 2*rjk0305 3 1 2 4 5 rf f _ l 4.12k r i s e n 1.27k cboot 0.22f cout 2*6tpf330m9l; 4*100f; 4*1f rconf 11.8k ql 2*rjk0301 3 1 2 4 5 ren_u 68.1k cpll 2.2nf c i s e t 1nf cvin 2.2f rfb2 787 cp l l _ h 390pf ren_l 10k rram p 140k rpll 5.11k cfb2 33nf rpcc 2.2 ? vin vout ros2 2k rfb4 3k cv cc1 2.2f c1 0.22f cpvcc1 4.7f lout1 320nh, 0.53m ? , 2 1 cvin2 4*10f rfb5 49.9 ? r1 2.8k rvin1 2 ? cfb4 2.2nf cfb5 8.2nf rss1 18.2k rfb6 3k 19 20 1 6 5 21 7 22 24 23 1 7 3 2 1 4 1 5 1 4 6 9 10 11 12 1 3 8 1 8 25 rff_h1 33.2k ri s e t 1 10k ros3 2k qh1 2*rjk0305 3 1 2 4 5 rf f _ l 1 4.12k r i s e n1 1.27k cboot1 0.22f cout1 2*6tpf330m9l; rconf1 11.8k ql1 2*rjk0301 3 1 2 4 5 ren_u1 68.1k cpll1 2.2nf ci s e t 1 1nf cvin32.2f rfb7 787 cp l l _ h 1 390pf ren_l1 10k r ram p 1 140k rpll1 5.11k cfb6 33nf rpcc1 2.2 ? rc s h 1 0 0 ? c c s h 1 0 0 p f r c s h 1 1 0 0 ? cc s h 1 1 0 0 p f u1 isl8115frtz iset ishare rg nd ram p pll_comp vin conf ss clkout f b v cc e n i s e nb v m o n f s e t p g o o d v f f ugate phase pvcc lgate i s e na boot c o m p gnd pa1513-321 u2 isl8115frtz iset ishare r g nd r am p pll_comp vin conf ss clkout f b v cc e n i s e nb v m o n f s e t p g o o d v f f ugate phase pvcc lgate i s e na boot co m p gnd 4*100f; 4*1f
isl8115 fn8272 rev 1.00 page 5 of 24 september 23, 2013 block diagram vcc 3 pvcc vin internal series linear regulator boot ugate phase lgate pvcc 10k 40k gate control logic 7 power-on reset (por) 11 over-temperature protection (otp) 8 9 10 12 5 soft-start and fault logic controller saw pwm non-linear control vmon fb e/a rgnd digital soft-start vref 17 ss comp 18 pgood vmon x1.15 uv ov_l ov_h x1.20 x1.10 x0.90 x0.50 15 4 isena isenb current mirror 13 14 current share block 20 ishare 5xi sen + 50a ocp 1.4v peak current limit 20a ish_corr1 ish_corr2 ish_corr1 oscillator generator decoder 21 6 1 23 vff pll_comp fset clkout 22 conf mode saw ov_h ov_l uv ocp/ucp 1.22v en 2 ep gnd ramp 16 ocp 24 ss-code ss-code 8 cycle-by-cycle 4.7f 2.2f 2.2 1.135a isen isen dem isen h i c c u p 0.25v ucp 0.225v ish_corr2 19 iset ciset
isl8115 fn8272 rev 1.00 page 6 of 24 september 23, 2013 pin configuration isl8115 (24 ld 4x4 qfn) top view en boot ugate phase pvcc lgate vin gnd clkout fb iset pgood 1 2 3 4 5 6 78 910 15 14 13 17 16 20 19 22 21 23 isena vcc comp 11 12 18 24 isenb conf rgnd vmon ishare pll_comp vff ss ramp fset functional pin descriptions pin number symbol description 1 fset placing a resistor (r fset ) from this pin to gnd to adjust the switching frequency. input an external clock signal to this pi n and the internal oscillator synchronizes with the leading edge of the input signal. 2 en the input voltage to this pin is compared with a precision 1. 22v reference. tie this pin to ground to disable the part. tie this pin to vin through a resistor divide r to realize undervoltage lock-out. 3 vcc this pin provides power for the analog circuitry. connect th is pin to a 2.97v to 5.15v bias through a recommended rc filter . this pin can be powered up by the internal or external linear regulator. a 2.2f filter capacitor is recommended to connect closely to the pin. 4 pgood provides an open drain power-good signal when the voltage at vmon is within 10% of nominal output regulation point after soft-start is complete. 5 ramp a resistor to gnd to set the sawtooth ramp. select the resistor value to make the ramp amplitude the same as the voltage on vff. refer to voltage feedforward section on page 15. 6 vff pin for input voltage feed-forward. the voltage at this pin se ts the internal oscillator ramp peak-to-peak amplitude at 1xv ff. a resistor divider network from input voltag e to this pin is required and an additional decoupling capacitor may be required at this pin in noisy input environments. make sure vff is in the range of the clamp voltage (0.53v to 2.59v) specified in ?electrical specifications? on page 9. 7 vin this pin should be tied directly to the input rail when usin g the internal linear regulator. it provides power to the inter nal linear drive circuitry. 8 boot this pin provides the bootstra p bias for the high-side driver. 9 ugate this pin provides the drive signals for the high-side devices and should be connected to the high-side mosfets? gates. 10 phase connect this pin to the source of the high-side mosfets and the drain of the lo w-side mosfets. this pin represents the r eturn path for the high-side gate drivers. 11 pvcc connect a 4.7f capacitor closely to this pin. this pin is the output of the internal series linear regulator. it provide s the bias for both low-side and high-side drivers. its operational voltage range is 2.97v to 5.3v. when the input supply is 5v, this pin should be tied directly to vin to eliminate the dropout voltage in the internal linear regulator. r ramp t s 275ns C 310pf ? ----------------------------- ts ; 1 f sw ------------ ==
isl8115 fn8272 rev 1.00 page 7 of 24 september 23, 2013 12 lgate this pin provides the drive for the low-side devices and should be connected to the lower mosfets? gates. 13 isena the positive input of the curr ent sensing amplifier. provide dcr, or precision resistor current sensing. 14 isenb the negative input of the current sensing amplifier. provide dcr, or precision resistor current sensing. 15 vmon this pin monitors the regulator?s output for ov and uv pr otection. pgood refers to the voltage on vmon. connect a resisto r divider from vout to rgnd, with the same ra tio as the fb resistor divider. it is no t recommended to share the resistor divider for both fb and vmon; the response to a fault may not be as qu ick or robust. the voltage on this pin is also monitored for the non-linear control. 16 rgnd pin for remote ground sensing. there? s a current sourcing out from rgnd if is et voltage is lower than ishare in the multi-phase configuration. a typical 100 resistor is required connected between rgnd and negative terminal of the load. 17 fb fb is the inverting input of the error amplifier. this pin is connected to the feedback resistor divider and provides the v oltage feedback signal for the controller. 18 comp this pin is the error amplifier?s output. it should be co nnected to the fb pin through a desired compensation network. th e lower limit of the voltage at comp is 0.85v. 19 iset this pin sources a current equal to 5 times i sen with 50a offset. connect r iset to the pin to adjust the ocp trigger point. parallel c iset with r iset to obtain the average output current signal at this pin. the voltage v iset set by an external resistor r iset represents the sensed current for the controller which compares with the intern al reference to implement over current protection. refer to the ??average overcurrent protection? on page 18. 20 ishare this pin is used for current sharing purpose and is confi gured to the current share bus re presenting all module?s refer ence current. the voltage v ishare represents the highest voltage of v iset of all active isl8115(s) that connected together to the current share bus. float in sing le phase operation. pulling this pin low will disable the isl8115. 21 pll_comp compensation pin for the internal pll circuit. a compensation network shows in the typical application diagram is req uired. r pll (5.11k ); c pll (2.2nf); c pll_h (390pf) are recommended. 22 conf a resistor at this pin is used to set: 1.) enable or di sable diode emulation mode, and 2) phase delay of clock out signal with respect to input clock signal. see table 1 for the resistor values. 23 clkout this pin provides clock signal to synchronize with other isl8115(s). the phase delay of the clkout with respect to the external clock signal is co nfigured through conf pin. 24 ss a resistor connected from this pin to ground is used to se lect the length of soft-start period. see table 2 for the resisto r values. 25 gnd all voltage levels are referenced to this pad. this pad pr ovides a return path for the low side mosfet drivers and interna l power circuitries as well as analog signals. connect this pad to the board ground with the shortest possible path (9 vias to the internal ground plane, placed on the soldering pad are recommended). functional pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # isl8115frtz 81 15frtz -40 to +125 24 ld exposed pad 4x4 tqfn l24.4x4f isl8115eval1z 12v to 1.5v/30a evaluation board ISL8115EVAL2Z 28v to 5v/20a evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl8115 . for more information on msl please see techbrief tb363 .
isl8115 fn8272 rev 1.00 page 8 of 24 september 23, 2013 absolute maximum rating s thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 38v pvcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v pvcc to vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1v to +1v boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +44v phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +41v phase voltage transient (20ns max) . . . . . . . . . . . . . . . . . . . . . . . gnd - 2v boot to phase voltage, boot-phase . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v lgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v lgate voltage transient (20ns max) . . . . . . . . . . . . . . . . . . . . . . gnd - 2.6v isena, isenb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.675v voltage on all other pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc + 0.3v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 250v latch up (tested per jesd-78b; class 1, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 24 ld qfn package (note 5). . . . . . . . . . . . 39 3.5 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c input voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.97v to 36v driver bias voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.97v to 5.5v signal bias voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.97v to 5.5v boot-to-phase voltage (overcharged), boot- phase. . . . . . . . . . . . . . . <6v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. unless otherwise specified, voltages are from the indicated pins to gnd 5. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions (v in = 12v; v cc = pvcc = 5.15v; f sw = 500khz; en = high), unless otherwise noted . boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test conditions min (note 7) typ max (note 7) units power supply i q_vin nominal supply vin current ugate = lgate = open 10 15 ma v in = 3.3v; v cc = pvcc; ugate = lgate = open 10 15 ma i q_vin_disable disable supply vin current en = 0v, v in = 24v 17 25 a i pvcc_disable pvcc shutdown current (sinking) en = 0v, pvcc = v in = 5.2v 1.0 a i vcc_disable vcc shutdown current (sinking) en = 0v, v cc = v in = 5.2v 1.0 a internal linear regulator pvcc pvcc voltage level i pvcc = 0ma to 50 ma 5.0 5.15 5.3 v i pvcc_limit output current limit v cc = pvcc = 3v; v in = 5.4v 85 140 ma r lin saturated equivalent impedance p-channel mosfet; v in = 5v 7 power-on reset rising vcc threshold 2.88 2.95 v vcc por hysteresis 170 mv rising pvcc threshold 2.88 2.95 v pvcc por hysteresis 170 mv enable turn-on threshold voltage 1.12 1.22 1.32 v i en_hys enable hysteresis 65 mv oscillator oscillator frequency range 150 1500 khz oscillator frequency r fset = 165k 135 150 165 khz
isl8115 fn8272 rev 1.00 page 9 of 24 september 23, 2013 oscillator frequency r fset = 47.8k 450 500 550 khz oscillator frequency r fset = 14.54k 1350 1500 1650 khz oscillator frequency total variation vcc = 5.15v, from 150khz to 1500khz -10 +10 % frequency synchronization range 150 1500 khz input signal duty cycle apply a input clock signal on fset pin 10 90 % clkout h clock output high i = 500a (sourcing) 4.9 v clkout l clock output low i = 500a (sinking) 0.3 v clkout tr clock output rise time c load = 100pf 27 ns clkout tf clock output fall time c load = 100pf 27 ns sawtooth ramp v sramp_offset sawtooth ramp offset r ramp = (ts-275n)/30p 1 v v sramp_max sawtooth ramp peak clamp value v cc -1.2v v g sramp linear gain of sawtooth ramp over v ff g ramp = dv ramp_pk-pk /v ff r ramp = (ts-275n)/30p 1v/v v sramp_pk-pk sawtooth ramp peak-to-peak voltage v cc = 5.15v; vff = 1v 1 v v ramp_max upper clamp voltage of ramp pin 2.59 2.98 3.36 v v ramp_min lower clamp voltage of ramp pin 0.48 0.5 0.53 v pwm minimum lgate on-time 150 200 250 ns reference accuracy v fb voltage on fb 0.6 v accuracy from -40c to +125c -1.0 +1.0 % accuracy from -40c to +105c -0.7 +0.7 % error amplifier dc gain r l = 10k, c l = 1pf at comp pin 98 db ugbw unity gain-bandwidth r l = 10k, c l = 1pf at comp pin 25 mhz output minimum voltage swing 0.85 v output maximum voltage swing v cc -0.8 v sr_ea output slew rate r l = 10k, c l = 1pf at comp pin 20 v/s i fb fb input current 20 na i comp output source/sink current 3 ma effective rgnd range with respect to gnd 200 mv gate driver r ugate_source upper drive source resistance 45ma source current 1.2 r ugate_sink upper drive sink resistance 45ma sink current 0.55 r lgate_source lower drive source resistance 45ma source current 0.9 r lgate_sink lower drive sink resistance 45ma sink current 0.4 ugate to phase internal resistor 10 k lgate to gnd internal resistor 40 k electrical specifications recommended operating conditions (v in = 12v; v cc = pvcc = 5.15v; f sw = 500khz; en = high), unless otherwise noted . boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 7) typ max (note 7) units
isl8115 fn8272 rev 1.00 page 10 of 24 september 23, 2013 current sense amplifier dc gain 70 db unity gain-bandwidth 5mhz isena pin input current 10 na input common mode range v in > 9v -0.2 6.375 v input offset -0.6 0.6 mv differential current sense voltage range r isen = 2k -8 40 mv i set_offset iset offset current 44 50 55 a i dem_threshold isen threshold of dem r isen = 2k 0.38 1.135 2.76 a overcurrent protection i oc isen overcurrent limit v cc = 5.15v 17.6 20 22.4 a v cc = 2.97v to 5.15v 20 a v iset_oc iset pin oc threshold v cc = 2.97v to 5.15v 1.40 v v cc = 5.15v 1.35 1.40 1.45 v iset pin under current threshold 0.22 0.25 0.28 v ishare pin fault threshold 0.22 0.225 0.24 v ishare pull-down voltage capability i share = 500a 0.2 v power good monitor and under/overvoltage protection v pg- power-good lower threshold voltage from vmon to rgnd; ~3 clock cycles noise filter 0.51 0.54 0.57 v v pg+ power-good upper threshold voltage from vmon to rgnd; ~3 clock cycles noise filter 0.63 0.66 0.69 v pgood low output voltage i pgood = 2ma 0.35 v under/over voltage protection with vmon v ov_nonlatch overvoltage non-latching off threshold voltage from vmon to rgnd; above the power-good upper threshold 30 mv v ov_latch overvoltage latching off threshold voltage from vmon to rgnd; above the ov non-latching up threshold 30 mv overvoltage lgate release trip point voltage from vmon to rgnd 0.51 v v uv undervoltage protection trip point voltage from vmon to rgnd; after soft-start completed 0.3 v v uv undervoltage protection trip point hysteresis 0.032 v non-linear control offset of the non-linear control refer to figure 23 20 mv over-temperature protection t otp over-temperature protection trip point 160 c otp release threshold 145 c note: 7. parameters with min and/or max limits ar e 100% tested at +25c, unless otherwise sp ecified. temperature limits established by characterization and are not production tested electrical specifications recommended operating conditions (v in = 12v; v cc = pvcc = 5.15v; f sw = 500khz; en = high), unless otherwise noted . boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 7) typ max (note 7) units
isl8115 fn8272 rev 1.00 page 11 of 24 september 23, 2013 typical performance curves unless otherwise stated, all curves were tested with example circuit in figure 1. figure 4. efficiency at 12v input, 1.5v output figure 5. efficiency at 5v input, 1.5v output figure 6. efficiency vs load current at 12v input f igure 7. efficiency vs load current at 5v input figure 8. line regulation, v out = 1.5v, i o = 20a figure 9. load regulation, v in = 12v, v out = 1.5v 70 75 80 85 90 95 0 5 10 15 20 efficiency (%) output current (a) ccm_v in = 12v f s = 220khz 70 75 80 85 90 95 0 5 10 15 20 ccm_v in = 5v efficiency (%) output current (a) f s = 220khz 30 40 50 60 70 80 90 0.5 1.5 2.5 3.5 ccm_v in = 12v dem_v in = 12v efficiency (%) output current (a) f s = 220khz 30 40 50 60 70 80 90 100 0.5 1.5 2.5 3.5 ccm_v in = 5v dem_v in = 5v efficiency (%) output current (a) f s = 220khz -0.020 -0.018 -0.016 -0.014 -0.012 -0.010 10 12 14 16 ? output voltage (%) input voltage (v) -0.00080 -0.00070 -0.00060 -0.00050 -0.00040 -0.00030 -0.00020 -0.00010 0.00000 0 5 10 15 20 25 35 output voltage (%) output current (a) 30
isl8115 fn8272 rev 1.00 page 12 of 24 september 23, 2013 figure 10. full load start-up figure 11. pre-bias start-up figure 12. hiccup ocp figure 13. transient response 2a/s figure 14. transient response 2a/s figure 15 . current sharing with 2-phase configuration typical performance curves unless otherwise stated, all curves were tested with example circuit in figure 1. (continued) en: 500mv/div i out : 10a/div v out : 500mv/div ss: 500mv/div 5ms/div v out : 500mv/div phase: 5v/div comp: 500mv/div en: 500mv/div i out : 20a/div v out : 1v/div phase: 10v/div 10ms/div i out : 10a/div 20s/div v out : 50mv/div (ac) v out : 50mv/div (ac) i out : 10a/div 20s/div il1: 4a/div il2: 4a/div iset2: 200mv/div iset1: 200mv/div
isl8115 fn8272 rev 1.00 page 13 of 24 september 23, 2013 figure 16. shutdown current vs temperature fig ure 17. overcurrent threshold vs temperature figure 18. feedback voltage reference vs temp erature figure 19. dead time vs temperature figure 20. frequency vs temperature figure 21. frequency vs r fset typical performance curves unless otherwise stated, all curves were tested with example circuit in figure 1. (continued) 17.05 17.10 17.15 17.20 17.25 17.30 17.35 17.40 17.45 17.50 -50 -25 0 25 50 75 100 125 i q_vin_disable (a) temperature (c) v in = 24v 21.15 21.20 21.25 21.30 21.35 21.40 21.45 21.50 21.55 -50 -25 0 25 50 75 100 125 i oc (a) temperature (c) 0.5980 0.5985 0.5990 0.5995 0.6000 0.6005 -50 -25 0 25 50 75 100 125 v ref (v) temperature (c) 0 5 10 15 20 25 30 35 40 45 -50-25 0 255075100125 t d (ns) temperature (c) 3.3v input 12v input 497.60 497.80 498.00 498.20 498.40 498.60 498.80 499.00 499.20 499.40 499.60 -50 -25 0 25 50 75 100 125 r fset = 47.8k frequency (khz) temperature (c) 10 30 50 70 90 110 130 150 170 190 150 350 550 750 950 1150 1350 1550 r fset (k) frequency (khz)
isl8115 fn8272 rev 1.00 page 14 of 24 september 23, 2013 functional description functional overview the isl8115 is a synchronous buck pwm controller with current sharing capability. the current sharing function allows multiple modules to be connected in parallel to achieve higher output current. the controller also features multi-phase operation to reduce input and output ripple current, re sulting in fewer components and reduced output dissipation. utilizing voltage-mode control with input voltage feed-forward compensation, the isl8115 maintains a constant loop gain for optimal transient response, especia lly for applications with a wide input voltage range. initialization the isl8115 requires v cc and pvcc biased by a single supply. the power-on reset (por) function continually monitors the input supply voltages (pvcc and v cc ) and the voltage at en pin. with pvcc, v cc and en above their por thresholds, the ic will initialize a process to read the resistor value on the conf and ss pins. this process can take up to 2ms. failure to read the resistor values will stop the soft-start process. after successfully reading the resist or values on the conf and ss pins, there is another 1ms delay for the pll. if the system voltage drops below the falling por threshold, then ugate and lgate are forced off. also ishare is pulled low. enable and input voltage uvlo when the voltage on en pin is gr eater than the 1.22v threshold, the controller is enabled. if th e en voltage is less than 1.22v minus the hysteresis (typical 65mv), the controller is disabled. the en pin can be used as a voltage monitor for the input undervoltage lock-out by connecting the en pin to the input rail through a resistor divider. pre-bias startup a pre-bias voltage may exist at the output before the controller is enabled. the isl8115 can support a pre-bias startup condition by keeping ugate and lgate off until the internal soft-start voltage exceeds the feedback voltage. this feature prevents the output voltage from discharging through the lower mosfet during the soft-start. setting conf pin a resistor connected from the co nf pin to ground is used to: ? enable or disable diode emulation mode (dem) after soft-start. ? set the phase delay of clkout with respect to an external clock signal applie d to the fset pin. use a resistor with 1% tolerance on the conf pin. setting ss pin a resistor connected from the ss pin to ground is used to set the length of the output soft-start time. the internal soft-start dac operates with and internal 2mhz clock. the value of the resistor on this pin set number on steps for the soft-start. the resistor value and the corresponding soft-start duration is shown in table 2. use a resistor with 1% tolerance on the ss pin. when using multiple isl8115s in parallel module configuration, all soft-start times must be set to the same value. table 1. resistor values to set conf pin phase delay ( ) dem 1% tolerance resistor value (k ) 0 enable 46.4 60 73.2 90 105 120 137 180 11.8 240 18.2 270 26.1 300 34 0disable (force ccm) 2.94 60 4.53 90 6.49 120 8.66 180 0.732 240 1.13 270 1.62 300 2.15 table 2. resistor values to set soft-start time 1% tolerance resistor value (k ) soft-start time (ms) 46.4 0.4 73.2 0.8 105 1.2 137 2.2 11.8 4.8 18.2 8.8 26.1 12.8 34 25.6
isl8115 fn8272 rev 1.00 page 15 of 24 september 23, 2013 frequency setting the switching frequency is set by the r fset connected between the fset pin and ground. figure 21 shows the typical r fset vs frequency variation curve. equation 1 illustrates the relationship between r fset and switching frequency. to synchronize with an external cl ock, apply a clock signal in the programmable oscillator range of 150khz to 1.5mhz to the fset pin. a duty cycle in the range of 10% to 90% is required. voltage feed-forward the voltage applied to the vff pi n can adjust the amplitude of the internal sawtooth ramp. it is recommended to set the amplitude equal to v ff . this helps to maintain a constant gain contributed by the modulator and the input voltage to achieve optimum loop response over a wide input voltage range. figure 22 shows the feed-forward circuits. v ff voltage is clamped betwee n 0.5v (typical) and v cc -2.2v (typical). to make the feed forward work for all input voltage, the voltage on vff pin should be designed within this range. the peak-to-peak amplitude of the sawtooth yields as: where: according to the equations 2 and 3, design the resistor at the ramp pin to make the amplitude of sawtooth equal to v ff . for example, select 113k for r fset to achieve 220khz switching frequency and 140k for r ramp to make the v ramp_pk_pk = v ff . the sawtooth ramp offset voltage is 1v and the peak of the sawtooth is to v ff +1v. non linear control in order to respond faster to a load step, non-linear control has been introduced in isl8115. if th e feedback voltage at vmon is greater than the voltage of the previous cycle plus 20mv (typical), the lg turns on immediately without waiting for the next clock signal. this function he lps to improve the transient response especially for a controller with leading-edge modulator. power-good the power-good comparator monitors the voltage on the vmon pin. the trip points are shown in figure 24. power-good will not be asserted until the completion of the soft-start cycle. the power-good pulls low when en is low or vmon is out of the threshold window. pgood stays high until the fault exists for three consecutive clock cycles. r fset 25 9 ? 10 1 fsw ----------- 85 9 C ? 10 C ?? ?? ? = (eq. 1) ideal diode ideal diode 3xi_discharge 1v vcc-2.2v rramp vramp_peak vin 0.5v 10pf i_discharge + - vramp_pk_pk vramp_pk_pk 275ns vramp_peak ts vff ramp fsw + - + - figure 22. feed-forward circuitry v ramp pk C pk C i disch e arg t s 275ns C 10pf ----------------------------- ? = (eq. 2) i disch e arg v ff 3r ramp --------------------- = (eq. 3) t s 1 f sw ---------- = r ramp t s 275ns C 3 10pf ? ----------------------------- = (eq. 4) turn on lg fsw vmon + - + - 20mv figure 23. non-linear control circuit figure 24. pgood circuit x1.10 x0.90 vmon end of ss pgood 3 clock cycles filter vref oc, oc, uv and ot
isl8115 fn8272 rev 1.00 page 16 of 24 september 23, 2013 undervoltage and overvoltage protection the undervoltage (uv) and overvoltage (ov) protection circuitry monitors the voltage on the vmon pin. the uv functionality is not enable d until the end of soft-start. if the vmon drops below 50% of the 0.6v internal reference, the controller goes into hiccup mode and recovers until vmon rises up to 0.332v. isl8115 has 2 level ov thresholds: 115% (non-latch), and 120% (latch). in an ov event with vmon between 115% and 120%, the high-side mosfet is turned off, while the low-side mosfet turns on. at the same time pgood is also pulled down. when the vmon voltage drops to 85% of re ference voltage, the lgate is turned off, then hiccup restart occurs. an ov event (v out > 120%) causes the high-side mosfet to latch off permanently, while the low-si de mosfet turns on and then turns off after the output voltage drops below 85%. at the same time, the pgood and ishare are also latched low. the latch condition can be reset only by re-cycling v cc or en. por overvoltage protection (por-ovp) when both the vcc and pvcc are below the por thresholds, the ugate is low and lgate is floating (high impedance). en has no control over lgate when below por. when above por, the lgate will toggle with its pwm pulses. an external 10k resistor can be placed between the phase and lgate node to implement a pre-por-ovp circuit. the output of the converter is equal to the phase node voltage via output inductor and then is effectively clamped to the low-side mosfet?s gate threshold voltage, which provides some protection to the load if the upper mosfet(s) is shorted during start-up, shutdown, or normal operations. for complete protection, the low-side mosfet should have a gate threshold that is much smaller than the maximum voltage rating of the load. the pre-por-ovp works against pre-biased start-up when pre-charged output voltage is hi gher than the threshold of the low-side mosfet. over-temperature protection (otp) when the junction temperature of the ic is greater than +160c (typically), the ugate and lgate are forced off. the ishare and pgood pins are forced low indica ting a fault. in a multi-phase configuration, this pulls the ishare bus low and informs other channels to turn off. all connected ishare pins stay low, but release after the ic?s junction temperature drops below the +15c hysteresis (typical). the device now starts the initialization process of reading th e config and ss resistors, pll locking, and soft-start. inductor current sensing the isl8115 supports inductor dcr sensing techniques up to 5.5v output voltage, as shown in figure 25. an inductor?s winding is characteri stic of a distributed resistance as measured by the dcr (direct current resistance) parameter. consider the inductor dcr as a separate lumped quantity, as shown in figure 25. the inductor current, i l , will also pass through the dcr. equation 5 shows the s-domain equivalent voltage across the inductor v l . a simple r-c network across th e inductor extracts the dcr voltage, as shown in figure 25. the voltage on the capacitor v c , can be shown to be proportion al to the inductor current i l , see equation 6. if the r-c network components ar e selected such that the rc time constant (= r*c) matches the inductor time constant (= l/dcr), the voltage across the capacitor v c is equal to the voltage drop across the dcr, i.e. , proportional to the inductor current. the value of r should be as small as feasible for best signal-to-noise ratio. make sure the resistor package size is appropriate for the power dissipated and include this loss in efficiency calculations. figure 25. dcr sensing configuration i set - + isena isl8115 v in isenb ugate r isen dcr l inductor r v out c out +v c (s) - c i l s ?? - + v l phase lgate internal circuit isen current mirror v l i l sl dcr + ? ?? ? = (eq. 5) v c s l dcr ------------- ? 1 + ?? ?? dcr i l ? ?? ? src 1 + ? ?? --------------------------------------------------------------- ----- - = (eq. 6)
isl8115 fn8272 rev 1.00 page 17 of 24 september 23, 2013 in calculating the minimum value of r, the average voltage across c (average of i l dcr product) is small and can be neglected. therefore, the minimum value of r may be approximated equation 7: , where p r-pkg is the maximum power dissipation specification for the resistor package and is the derating factor for the same parameter (e.g., p r-pkg = 0.063w for 0402 package, = 80% @ +85c). k is the margin factor, al so to limit temperature raise in the resistor package, recommend using 0.4. once r min has been calculated, solve for the maximum value of c from equation 8 : next, choose the next-lowest readily available value. then substitute the chosen value into the same equation and re-calculate the value of r. choos e a 1% resistor standard value closest to this re-calculated value of r. for example, when v in- max = 14.4v, v out = 2.5v, l = 1mh and dcr = 1.5m , with 0402 package equation 7 yields r min of 1476 and equation 8 yields c max of 0.45f. choose 0.39f and re-calculate, the resistor yields 1.69k ? . with the internal low-offset current amplifier, the capacitor voltage vc is replicated across the sense resistor r isen . therefore, the current out of isenb pin, i sen , is proportional to the inductor current. peak current limit the isl8115 contains a peak curr ent limit circuit to protect the converter. when a peak current limit occurs, the ug is turned off immediately. an internal counter begins to record the number of oc events detected. two consecutive clock cycles without a current limit will reset the counte r. if 8 consecutive clock cycles of overcurrent is detected, the isl8115 enters into a hiccup mode. the isl8115 operation during the peak current limit event is illustrated in figure 26. the sensed current signal and pe ak current signal in figure 25 can be derived by the following equations: r min dv in max C v out C ?? ? 2 1d C ?? v out 2 ? + kp ? rpkg C ? p ? --------------------------------------------------------------- ---------------------------------------------- - = (eq. 7) ? p ? p c max l r min dcr ? ------------------------------- - = (eq. 8) i sen i l dcr ? r isen ---------------------- - = (eq. 9) i sen pk C i l v out l ----------- - 1d C 2f sw -------------- ? + ?? ?? ?? dcr ? r isen --------------------------------------------------------------- --- = (eq. 10) 1 23 1 23 456 7 8 hiccup phase clock current limit 20a (typical) isen 0a ug off no trigger in two consecutive cycles will reset the counter figure 26. current limit timing
isl8115 fn8272 rev 1.00 page 18 of 24 september 23, 2013 average overcurrent protection the isl8115 provides an average overcurrent protection circuit to protect the converter during an overcurrent fault. the voltage on pin iset represents the average inductor current signal which compares with an internal reference of 1.4v to implement positive overcurrent protection and 0.25v for negative current protection. if th e overcurrent event is detected, the isl8115 will enter hiccup mode. this consists of a 10ms shut down and then a restart. the voltage on pin iset can be obtained from equation 11. the circuit of average ocp is shown in figure 27. select a suitable r iset for setting the ocp trigger point. also, a filer capacitor c iset is required in parallel with r iset to get the average inductor current signal. generally, set the average ocp trigger point lower than the peak current limit. for example, l = 2.5h; dcr = 1.6m ; i out = 20a; di = 8a; f sw = 220khz. to set 24a as the ou tput peak current limit. r sen can be derived by: considering dcr increases as th e temperature rises. select 3k (2.24k x 1.34) for r sen . to set 22a for the average ocp, the value of r iset can be yield as: to filter the inductor ripple current and achieve the average inductor current signal from iset , the roll off frequency of the low pass filter should be much lowe r than the switching frequency. capacitor at iset c iset is obtained by equation 14: select a 1nf capacitor for c iset . dem diode emulation allows for higher converter efficiency under light load situations. with diode emul ation active, the isl8115 will detect the zero current crossing of the output inductor and turn off lgate. this ensures that discontinuous conduction mode (dcm) is achieved. this prevents the low side mosfet from sinking current and discharging of the output during pre-biased startup. dem can only be disabled after soft-start. please refer to the ?electrical specifications? ta ble on page 10 for the threshold of dem. current sharing the isl8115 can support up to 6 phase operation. connecting the ishare pins together allows for communication between the phases. in a single phase applicat ion, the voltage on the ishare pin follows the iset voltage and the ishare pin can be floated. however, in multi-phase applicat ions, the voltage on the ishare bus represents the highest iset voltage of all phases. this voltage becomes the current reference of each phase. figure 28 illustrates the relation between ishare and iset. the voltage difference between ishare and iset will create two correction currents (see figure 29). one is ish_corr1 which makes the comp voltage increase and the other is ish_corr2 which makes the rgnd voltage in crease. a resistor (typically 100 ) connected between rgnd and the output capacitor ground is required. the correctio n currents make the duty cycle increase thereby making the voltag e at iset track the voltage at ishare within 10mv of offset. v iset 5i sen 50 ? a + ?? r iset ? = (eq. 11) multiplier isen 5 + 5xisen 50a riset ciset 1.4v oc hiccup iset + - + - 0.25v figure 27. average ocp circuit r sen i oc 1 2 -- - di + ?? ?? dcr ? 20ua ------------------------------------------------- 24a 4a + ?? 1.6m ? ? 20ua ------------------------------------------------------ - 2.24k ? == = (eq. 12) r iset 1.4v 22a 1.34dcr ? 3k ? ------------------------------------------- 550ua + ? --------------------------------------------------------------- ----------- 10.7k ? == (eq. 13) 1 2 ? r iset c iset ? ---------------------------------------------- 1 10 ------ f sw ? ? c iset 10 f sw ------------ 1 2 ? r iset ------------------------ - 0.68nf = ? ? (eq. 14) figure 28. current sensing block diagram r isen ` csa r iset v` + - v` isena isenb + vc - i sen iset iset ishare ishare bus i sen ? = ? vc r isen =i l xdcr phase vout r isen + - 10mv + + ishare iset - gm comp rgnd gain1 ish_corr1 gain2 ish_corr2 figure 29. current sharing block diagram
isl8115 fn8272 rev 1.00 page 19 of 24 september 23, 2013 figure 30 shows 3-phase operation. device 1 is the master and the remaining devices are synchronized and phase shifted. the phase shift can be set using the conf pin. the ishare bus remains low until the pll of all phases are locked. this assures that all phas es start up at the same time, thereby preventing an overcurrent condition. a 40k resistor is required between the ishare bus and ground. feedback compensation figure 31 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the reference voltage level. the error amplifier output (v ea ) is compared with the oscillator (osc) sawtooth waveform to provide a pulse-width modulated (pwm) signal with an amplitude of vin at the phase node. the pwm signal is smoothed by the output filter (l o and c o ). this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to- peak oscillator voltage ? v osc . figure 30. simplified multi-phase diagram rgnd en fset clkout rgnd en fset clkout rgnd en fset clkout r fset rcsr 100ohm rcsr 100ohm rcsr 100ohm vin module1 module2 module3 ishare ishare ishare r ishare 40kohm isl8115 isl8115 isl8115 figure 31. voltage- mode buck converter compensation design _ + z in z fb osc lo pwm comparator vin error amp reference v comp driver driver phase co esr vo c1 r2 c2 c3 r3 r1 r4 _ + _ + reference vo v comp fb isl8115 z fb z in detailed compensation components vout vref*(1+r1/r4) v osc ?
isl8115 fn8272 rev 1.00 page 20 of 24 september 23, 2013 modulator break frequency equations the compensation network consists of the error amplifier (internal to the isl8115) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180. the following equations relate to the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figure 31. use the following guidelines for locating the poles and zeros of the compensation network. compensation break frequency equations 1. pick gain (r2/r1) for desired converter bandwidth 2. place 1 st zero below filter?s double pole (~75% f lc ) 3. place 2 nd zero at filter?s double pole 4. place 1 st pole at the esr zero 5. place 2 nd pole at half the switching frequency 6. check gain against error amplifier?s open-loop gain 7. estimate phase margin - repeat if necessary figure 32 shows an asymptotic plot of the dc/dc converter?s gain vs frequency. the actual modulator gain has a high gain peak due to the high q factor of the ou tput filter and is not shown in figure 32. using the previously ment ioned guidelines should give a compensation gain similar to th e curve plotted. the open loop error amplifier gain bounds th e compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the loop gain is cons tructed on the log-log graph of figure 32 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to th e compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high ba ndwidth (bw) overall loop. a stable control loop has a gain cr ossing with -20db/decade slope and a phase margin greater than 45. include worst case component variations when determining phase margin. component selection guidelines output capacitor selection the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. selection of output ca pacitors is also dependent on the output inductor, thus some inductor analysis is required to select the output capacitors. one of the parameters limiting the converter?s response to a load transient is the time required for the inductor current to slew to its new level. the response time is the time interval required to slew the inductor current from an initial current value to the load current level. during this interval the difference between the inductor current and the transien t current level must be supplied by the output capacitor(s). mini mizing the response time can minimize the output capacitanc e required. also, if the load transient rise time is slower than the inductor response time, as in a hard drive or cd drive, it reduces the requirement on the output capacitor. the maximum capacitor value required to provide the full, rising step, transient load current duri ng the response time of the inductor is shown in equation 21: where c out is the output capacitor(s) required, l o is the output inductor, i tran is the transient load current step, v in is the input voltage, v o is output voltage, and dv out is the drop in output voltage allowed during the load transient. f lc 1 2 ? l o c o ? ? -------------------------------------- - = (eq. 15) f esr 1 2 ? esr c o ? ?? ? -------------------------------------------- - = (eq. 16) f z1 1 2 ? r ? 2c1 ? ---------------------------------- = (eq. 17) f p1 1 2 ? r2 ? c1 c2 ? c1 c2 + ---------------------- ?? ?? ? ------------------------------------------------------ - = (eq. 18) f z2 1 2 ? r1 r3 + ?? c3 ? ? ----------------------------------------------------- - = (eq. 19) f p2 = 1 2 ? r3 c3 ? ? ---------------------------------- (eq. 20) 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensation gain (db) frequency (hz) gain 20log (vin/dv osc ) modulator gain 20log (r 2 /r 1 ) loop gain figure 32. asymptotic bode plot of converter gain c out l o ?? i tran ?? 2 2v in v o C ?? dv out ?? ---------------------------------------------------------- - = (eq. 21)
isl8115 fn8272 rev 1.00 page 21 of 24 september 23, 2013 high frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (equivalent series resistance) an d voltage rating requirements as well as actual capacitance requirements. the output voltage ripple is due to the inductor ripple current and the esr of the output capacitors as defined by equation 22: high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load circuitry for specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications fo r the bulk capacitors. in most cases, multiple small-case electrolytic capacitors perform better than a single large-case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the co nverter?s response time to the load transient . the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current and output capacitor(s) esr. the ripple current is approximated by equation 23: increasing the value of inductan ce reduces the ripple current and voltage. however, the large in ductance values reduce the converter?s response time to a load transient. also, it always means more expensive and large size. input capacitor selection the important parameters for the bulk input capacitor(s) are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25x greater than the maximum input voltage and 1.5x is a conservative guideline. the ac rms input current varies with the load. the total rms current supplied by the input capacitance is given by equation 24: where, d is duty cycle of the buck converter. use a mix of input bypass capacitors to control the voltage ripple across the mosfets. use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors can be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. mosfet selection the logic level mosfets are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements, two n-channel mosfets for the buck converter. these mosfets should be selected based upon r ds(on) , gate supply requirements, and thermal management considerations. compared with other components, mosfets contribute significant power loss to the converter. power loss of high side fet includes switching losses, conduction losses and gate charge losses. low side fet contribute s conduction losses and gate charge losses too, also reverse recovery loss and loss of the body diode during dead time should be considered. power loss of high side mo sfet can be expressed as: where t sw is switching interval includes on and off intervals. q h is gate charge of the high side mosfet. power loss of low side mosfet derived as: where q rr is the total reverse recovery charge. q l is gate charge of the low side mosfet. layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or single point grounding. figure 33 shows the critical power components of the buck converter. to minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. the components shown in figure 33 should be located as close together as possible. please note that the capacitors c in and c o each represent numerous physical capacitors. locate the isl8115 within 3 inches of the mosfets, q 1 and q 2 . the circuit traces for the mosfets? gate and source connections from the isl8115 must be sized to handle up to 4a peak current. v ripple ? i l esr ?? = (eq. 22) ? i l v in v out C ?? v out ?? f s ?? l o ?? v in ?? --------------------------------------------------------- - = (eq. 23) i rmsx i o 2 dd 2 C ?? ? i l 2 12 ----------- - d + = (eq. 24) p h i o 2 i l ? 2 12 ----------- + ?? ?? ?? dr ds on ?? ? v in i o t sw f sw v in q h f sw ++ ? = (eq. 25) p l i o 2 i l ? 2 12 ----------- + ?? ?? ?? 1d C ?? r ds on ?? ? v in q rr f sw v in q l f sw ++ ? = (eq. 26)
isl8115 fn8272 rev 1.00 page 22 of 24 september 23, 2013 figure 34 shows the current sensing loop of the isl8115 which is a sensitive analog loop needs ?q uiet and clean environment?. to minimize the coupling from switching nodes, using differential pair as the sensing route. r should be located close to the inductor; c and risen should be close to the ic. general powerpad design considerations figure 35 is an example of how to use vias to remove heat from the ic. we recommend you fill the thermal pad area with vias. a typical via array would be to fill the thermal pad footprint with space, such that they are center on cent er 3x the radius apart from each other. keep the vias small but not so small that their inside diameter prevents solder wicking through the holes during reflow. connect all vias to the ground plane. it is important the vias have a low thermal resistance for ef ficient heat transfer. it is important to have a complete connection of the plated through-hole to each plane. figure 33. critical power train loop gnd l o c o lgate ugate phase q1 q2 v in v out return isl8115 c in load figure 34. current sensing loop isena isenb phase lo co risen r c vout isl8115 differential pair figure 35. pcb via pattern
fn8272 rev 1.00 page 23 of 24 september 23, 2013 isl8115 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2013. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change september 23, 2013 fn8272.1 initial release.
isl8115 fn8272 rev 1.00 page 24 of 24 september 23, 2013 package outline drawing l24.4x4f 24 lead thin quad flat no-lead plastic package rev 2, 1/11 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view compliant to jedec mo-220 vggd-8. 7. c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 4.00 (4x) 0.15 6 pin 1 index area 19 pin #1 24 2.50 20x 0.50 exp. dap 6 1 18 13 12 24x 0.400 0.10 7 6 2.50 0.75 0.05 see detail "x" seating plane 0.08 0.10 c c c ( 3.80 ) ( 2.50 ) ( 24 x 0.60) (24x 0.25) ( 20x 0.50) ( 3.80 ) ( 2.50) 0.10 24x 0.250 0.050 a mc b 4 2.50 0.05 sq. index area 0.25 min (4 sides)

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